The P4 language evades the limitation of fixed networking devices. It provides a way to describe a custom packet processing chain that involves parsing, matching and assembling modified packets. This abstraction allows for great decoupling of data plane and control plane, enabling new applications and more options in virtualization of networking resources. The language is target independent and can be mapped to CPUs, FPGAs, NPUs and ASICs. Our poster introduces an algorithm and tool that maps P4 to a general architecture of FPGA-based networking device. The whole device is automatically generated from P4 source code and the network architects don't need to write any FPGA HDL code. Several parameters, such as data width and pipeline depth, can be used to tune the generated circuit throughput, latency and area. Our results show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding. Network architects and device vendors are free to specify the exact behavior and bring new features even to the highest performance equipment. Overall, the P4 language, together with field programmable networking elements, lower vendor dependency, facilitate experimentation at scale and accelerate innovation in the networking.
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